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rev. 1.3 3/11 copyright ? 2011 by silicon labora tories si8410/20/21 si8410/20/21 iso pro l ow -p ower s ingle and d ual -c hannel d igital i solators features applications safety regulatory approvals description silicon lab's family of ultra-low-pow er digital isolators are cmos devices offering substantial data rate, prop agation delay, power, size, reliability, and external bom advantages when compared to legacy isolation technologies. the operating parameters of these products remain stable across wide temperature ranges throughout their service life. for ease of design, only vdd bypass capacitors are required. data rates up to 150 mbps are supported, and all devices achieve worst- case propagation delays of less than 10 ns. all products are safety certified by ul, csa, and vde and support withstand voltages of up to 2.5 kvrms. these devices are availa ble in an 8-pin narrow-body soic package. ? high-speed operation ?? dc to 150 mbps ? no start-up init ialization required ? wide operating supply voltage: 2.70?5.5 v ? ultra low power (typical) 5 v operation: ?? < 2.1 ma per channel at 1 mbps ?? < 6 ma per channel at 100 mbps 2.70 v operation: ?? < 1.8 ma per channel at 1 mbps ?? < 4 ma per channel at 100 mbps ? high electromagnetic immunity ? up to 2500 v rms isolation ? 60-year life at rated working voltage ? precise timing (typical) ?? <10 ns worst case ?? 1.5 ns pulse width distortion ?? 0.5 ns channel-channel skew ?? 2 ns propagation delay skew ?? 6 ns minimum pulse width ? transient immunity 25 kv/s ? wide temperature range ?? ?40 to 125 c at 150 mbps ? rohs-compliant packages ?? soic-8 narrow body ? industrial automation systems ? hybrid electric vehicles ? isolated switch mode supplies ? isolated adc, dac ? motor control ? power inverters ? communications systems ? ul 1577 recognized ?? up to 2500 v rms for 1 minute ? csa component notice 5a approval ?? iec 60950-1, 61010-1 (reinforced insulation ) ? vde certification conformity ?? iec 60747-5-2 (vde0884 part 2) ordering information: see page 25.
si8410/20/21 2 rev. 1.3
si8410/20/21 rev. 1.3 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2. eye diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 2.3. device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4. layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5. typical performance char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3. errata and design migration guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1. power supply bypass capacit ors (revision c and revision d) . . . . . . . . . . . . . . . . 23 3.2. latch up immunity (rev ision c only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. package outline: 8-pin narrow body so ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 7. land pattern: 8-pin narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
si8410/20/21 4 rev. 1.3 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit ambient operating temperature* t a 150 mbps, 15 pf, 5 v ?40 25 125 c supply voltage v dd1 2.70 ? 5.5 v v dd2 2.70 ? 5.5 v *note: the maximum ambient temperature is dependent upon data frequency, output loading, the number of operating channels, and supply voltage. table 2. absolute maximum ratings 1 parameter symbol min typ max unit storage temperature 2 t stg ?65 ? 150 c operating temperature t a ?40 ? 125 c supply voltage (revision c) 3 v dd1 , v dd2 ?0.5 ? 5.75 v supply voltage (revision d) 3 v dd1 , v dd2 ?0.5 ? 6.0 v input voltage v i ?0.5 ? v dd + 0.5 v output voltage v o ?0.5 ? v dd + 0.5 v output current drive channel i o ??10ma lead solder temperature (10 s) ? ? 260 c maximum isolation voltage (1 s) ? ? 3600 v rms notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. vde certifies storage temper ature from ?40 to 150 c. 3. see "5. ordering guide" on page 25 for more information.
si8410/20/21 rev. 1.3 5 table 3. electrical characteristics (v dd1 = 5 v 10%, v dd2 = 5 v 10%, t a =?40 to 125oc) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 4.8 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 1 z o ?8 5? ? dc supply current (all inputs 0 v or at supply) si8410ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 0.8 0.8 1.8 0.8 1.2 1.2 2.7 1.2 ma si8420ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.0 1.3 3.0 1.4 1.5 2.0 4.5 2.1 ma si8421ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.3 1.3 2.3 2.3 2.0 2.0 3.5 3.5 ma 1 mbps supply current (all inputs = 500 khz square wa ve, ci = 15 pf on all outputs) si8410ax, bx v dd1 v dd2 ? ? 1.3 0.9 2.0 1.4 ma si8420ax, bx v dd1 v dd2 ? ? 2.0 1.6 3.0 2.4 ma si8421ax, bx v dd1 v dd2 ? ? 1.9 1.9 2.9 2.9 ma notes: 1. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
si8410/20/21 6 rev. 1.3 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 1.3 1.2 2.0 1.8 ma si8420bx v dd1 v dd2 ? ? 2.0 2.1 3.0 3.2 ma si8421bx v dd1 v dd2 ? ? 2.2 2.2 3.3 3.3 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 1.4 4.6 2.1 5.8 ma si8420bx v dd1 v dd2 ? ? 2.2 9.2 3.3 11.5 ma si8421bx v dd1 v dd2 ? ? 5.8 5.8 7.3 7.3 ma timing characteristics si8410ax, si8420ax, si8421ax maximum data rate 0 ? 1.0 mbps minimum pulse width ? ? 250 ns propagation delay t phl , t plh see figure 1 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 1 ? ? 25 ns propagation delay skew 2 t psk(p-p) ? ? 40 ns channel-channel skew t psk ? ? 35 ns table 3. electrical characteristics (continued) (v dd1 = 5 v 10%, v dd2 = 5 v 10%, t a =?40 to 125oc) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
si8410/20/21 rev. 1.3 7 figure 1. propagation delay timing si8410bx, si8420bx, si8421bx maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.0 ns propagation delay t phl , t plh see figure 1 3.0 6.0 9.5 ns pulse width distortion |t plh - t phl | pwd see figure 1 ? 1.5 2.5 ns propagation delay skew 2 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 8n s all models output rise time t r c l = 15 pf ? 3.8 5.0 ns output fall time t f c l = 15 pf ? 2.8 3.7 ns common mode transient immunity cmti v i =v dd or 0 v ? 25 ? kv/s start-up time 3 t su ?1 54 0 s table 3. electrical characteristics (continued) (v dd1 = 5 v 10%, v dd2 = 5 v 10%, t a =?40 to 125oc) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output. typical input t plh t phl typical output t r t f 90% 10% 90% 10% 1.4 v 1.4 v
si8410/20/21 8 rev. 1.3 table 4. electrical characteristics (v dd1 = 3.3 v 10%, v dd2 = 3.3 v 10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 3.1 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 1 z o ?8 5? ? dc supply current (all inputs 0 v or at supply) si8410ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 0.8 0.8 1.8 0.8 1.2 1.2 2.7 1.2 ma si8420ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.0 1.3 3.0 1.4 1.5 2.0 4.5 2.1 ma si8421ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.3 1.3 2.3 2.3 2.0 2.0 3.5 3.5 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8410ax, bx v dd1 v dd2 ? ? 1.3 0.9 2.0 1.4 ma si8420ax, bx v dd1 v dd2 ? ? 2.0 1.6 3.0 2.4 ma si8421ax, bx v dd1 v dd2 ? ? 1.9 1.9 2.9 2.9 ma notes: 1. the nominal output impedance of an isol ator driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. start-up time is the time period from the a pplication of power to valid data at the output.
si8410/20/21 rev. 1.3 9 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 1.3 1.2 2.0 1.8 ma si8420bx v dd1 v dd2 ? ? 2.0 2.1 3.0 3.2 ma si8421bx v dd1 v dd2 ? ? 2.2 2.2 3.3 3.3 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 1.3 3.3 2.0 4.9 ma si8420bx v dd1 v dd2 ? ? 2.0 6.5 3.0 8.1 ma si8421bx v dd1 v dd2 ? ? 4.4 4.4 5.5 5.5 ma timing characteristics si8410ax, si8420ax, si8421ax maximum data rate 0?1.0mbps minimum pulse width ??250ns propagation delay t phl , t plh see figure 1 ? ? 35 ns pulse width distortion |t plh ? t phl | pwd see figure 1 ? ? 25 ns propagation delay skew 2 t psk(p-p) ? ? 40 ns channel-channel skew t psk ? ? 35 ns table 4. electrical characteristics (continued) (v dd1 = 3.3 v 10%, v dd2 = 3.3 v 10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isol ator driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. start-up time is the time period from the a pplication of power to valid data at the output.
si8410/20/21 10 rev. 1.3 si8410bx, si8420bx, si8421bx maximum data rate 0?1 5 0m b p s minimum pulse width ??6 . 0n s propagation delay t phl , t plh see figure 1 3.0 6.0 9.5 ns pulse width distortion |t plh ? t phl | pwd see figure 1 ? 1.5 2.5 ns propagation delay skew 2 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 8n s all models output rise time t r c l = 15 pf ? 4.3 6.1 ns output fall time t f c l = 15 pf ? 3.0 4.3 ns common mode transient immunity cmti v i =v dd or 0 v ? 25 ? kv/s start-up time 3 t su ?1 54 0 s table 4. electrical characteristics (continued) (v dd1 = 3.3 v 10%, v dd2 = 3.3 v 10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isol ator driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. start-up time is the time period from the a pplication of power to valid data at the output.
si8410/20/21 rev. 1.3 11 table 5. electrical characteristics 1 (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 c) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 2.3 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 2 z o ?8 5? ? dc supply current (all inputs 0 v or at supply) si8410ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 0.8 0.8 1.8 0.8 1.2 1.2 2.7 1.2 ma si8420ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.0 1.3 3.0 1.4 1.5 2.0 4.5 2.1 ma si8421ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.3 1.3 2.3 2.3 2.0 2.0 3.5 3.5 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8410ax, bx v dd1 v dd2 ? ? 1.3 0.9 2.0 1.4 ma si8420ax, bx v dd1 v dd2 ? ? 2.0 1.6 3.0 2.4 ma si8421ax, bx v dd1 v dd2 ? ? 1.9 1.9 2.9 2.9 ma notes: 1. specifications in this table are also valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. start-up time is the time period from the a pplication of power to valid data at the output.
si8410/20/21 12 rev. 1.3 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 1.3 1.2 2.0 1.8 ma si8420bx v dd1 v dd2 ? ? 2.0 2.1 3.0 3.2 ma si8421bx v dd1 v dd2 ? ? 2.2 2.2 3.3 3.3 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 1.3 2.7 2.0 4.0 ma si8420bx v dd1 v dd2 ? ? 2.0 5.2 3.0 6.5 ma si8421bx v dd1 v dd2 ? ? 3.7 3.7 4.6 4.6 ma timing characteristics si8410ax, si8420ax, si8421ax maximum data rate 0 ? 1.0 mbps minimum pulse width ? ? 250 ns propagation delay t phl , t plh see figure 1 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 1 ? ? 25 ns propagation delay skew 3 t psk(p-p) ? ? 40 ns channel-channel skew t psk ? ? 35 ns table 5. electrical characteristics 1 (continued) (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. specifications in this table are also valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. start-up time is the time period from the a pplication of power to valid data at the output.
si8410/20/21 rev. 1.3 13 si8410bx, si8420bx, si8421bx maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.0 ns propagation delay t phl , t plh see figure 1 3.0 6.0 9.5 ns pulse width distortion |t plh - t phl | pwd see figure 1 ? 1.5 2.5 ns propagation delay skew 3 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 8n s all models output rise time t r c l = 15 pf ? 4.8 6.5 ns output fall time t f c l = 15 pf ? 3.2 4.6 ns common mode transient immunity cmti v i =v dd or 0 v ? 25 ? kv/s start-up time 4 t su ?1 54 0 s table 6. regulatory information* csa the si84xx is certified under csa component acceptan ce notice 5a. for more details, see file 232873. 61010-1: up to 300 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. 60950-1: up to 130 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. vde the si84xx is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. 60747-5-2: up to 560 v peak for basic insulation working voltage. ul the si84xx is certified under ul1577 component recognition program. for more details, see file e257455. rated up to 2500 v rms isolation voltage for basic insulation. *note: regulatory certifications apply to 2.5 kv rms rated devices which are production tested to 3.0 kv rms for 1 sec. for more information, see "5. ordering guide" on page 25. table 5. electrical characteristics 1 (continued) (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. specifications in this table are also valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. start-up time is the time period from the a pplication of power to valid data at the output.
si8410/20/21 14 rev. 1.3 table 7. insulation and safety-related specifications parameter symbol test condition value unit nominal air gap (clearance) 1 l(io1) 4.9 mm nominal external tracking (creepage) 1 l(io2) 4.01 mm minimum internal gap (internal clearance) 0.008 mm tracking resistance (proof tracking index) pti iec60112 600 v rms erosion depth ed 0.040 mm resistance (input-output) 2 r io 10 12 ? capacitance (input-output) 2 c io f=1mhz 1.0 pf input capacitance 3 c i 4.0 pf notes: 1. the values in this table correspond to the nominal creepa ge and clearance values as detailed in "6. package outline: 8-pin narrow body soic" on page 26. vde certifies the clearance and creepage limits as 4.7 mm minimum for the nb soic-8 package. ul does not impose a clearance and cree page minimum for component level certifications. csa certifies the clearance and creepage limits as 3.9 mm minimum for the nb soic-8 package. 2. to determine resistance and capacitance, the si84xx is converted into a 2-terminal device. pins 1?4 are shorted together to form the first terminal and pins 5?8 are shorte d together to form the second terminal. the parameters are then measured between these two terminals. 3. measured from input pin to ground. table 8. iec 60664-1 (vde 0844 part 2) ratings parameter test conditions specification basic isolation group material group i installation classification rated mains voltages < 150 v rms i-iv rated mains voltages < 300 v rms i-iii rated mains voltages < 400 v rms i-ii rated mains voltages < 600 v rms i-ii
si8410/20/21 rev. 1.3 15 table 9. iec 60747-5-2 insulation characteristics for si84xxxb* parameter symbol test cond ition characteristic unit maximum working insulation voltage v iorm 560 v peak input to output test voltage v pr method b1 (v iorm x 1.875 = v pr , 100% production test, t m =1 sec, partial discharge < 5 pc) 1050 v peak transient overvoltage v iotm t = 60 sec 4000 v peak pollution degree (din vde 0110, table 1) 2 insulation resistance at t s , v io =500v r s >10 9 ? *note: maintenance of the safety data is ensu red by protective circuits. the si84xx provides a climate classification of 40/125/21. table 10. iec safety limiting values 1 parameter symbol test condition min typ max unit case temperature t s ? ? 150 c safety input, output, or supply current i s ? ja = 140 c/w, v i =5.5v, t j =150c, t a =25c ??160ma device power dissipation 2 p d ??150mw notes: 1. maximum value allowed in the event of a failure; also see the thermal derating curve in figure 2. 2. the si841x/2x is tested with vdd1 = vdd2 = 5.5 v, tj = 150 c, cl = 15 pf, input a 150 mbps 50% duty cycle square wave.
si8410/20/21 16 rev. 1.3 figure 2. (nb soic-8) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 11. thermal characteristics parameter symbol test condition min typ max unit ic junction-to-air thermal resistance ? ja ?140?c/w 0 200 150 100 50 400 200 100 0 case temperature (oc) safety-limiting values (ma) 320 300 v dd1 , v dd2 = 2.70 v v dd1 , v dd2 = 3.3 v v dd1 , v dd2 = 5.5 v 270 160
si8410/20/21 rev. 1.3 17 2. functional description 2.1. theory of operation the operation of an si84xx channel is analogous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple archit ecture provides a robust isolated data path and requires no special considerations or initializat ion at start-up. a simplified block diagra m for a single si84xx channel is shown in figure 3. figure 3. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driv er. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consum ption, and better immunity to magnetic fields. see figure 4 for more details. figure 4. modulation scheme rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver input signal output signal modulation signal
si8410/20/21 18 rev. 1.3 2.2. eye diagram figure 5 illustrates an eye-diagram take n on an si8410. for the data source, the test used an anritsu (mp1763c) pulse pattern generator set to 1000 ns/div. the output of the generator's clock and data from an si8410 were captured on an oscillosc ope. the results illustra te that data integrity was mainta ined even at the high data rate of 150 mbps. the results also show that 2 ns pulse wid th distortion and 250 ps peak jitter were exhibited. figure 5. eye diagram
si8410/20/21 rev. 1.3 19 2.3. device operation device behavior during start-up, normal operation, and shutdown is shown in table 12. table 12. si84xx logic operation table v i input 1,4 vddi state 1,2,3 vddo state 1,2,3 v o output 1,4 comments hp p h normal operation. lp p l x 5 up p l upon transition of vddi from unpowered to pow- ered, v o returns to the same state as v i in less than 1 s. x 5 p up undetermined upon transition of vddo from unpowered to pow- ered, v o returns to the same state as v i within 1s. notes: 1. vddi and vddo are the input and output power supplies. v i and v o are the respective input and output terminals. 2. powered (p) state is defined as 2.70 v < vdd < 5.5 v. 3. unpowered (up) state is defined as vdd = 0 v. 4. x = not applicable; h = logic high; l = logic low. 5. note that an i/o can power the die for a given side through an internal diode if its source has adequate current.
si8410/20/21 20 rev. 1.3 2.4. layout recommendations to ensure safety in the end us er application, high voltage circ uits (i.e., circuits with >30 v ac ) must be physically separated from the safety extra-low voltage circuits (selv is a circuit with <30 v ac ) by a certain distance (creepage/clearance). if a component, su ch as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). table 6 on page 13 and table 7 on page 14 detail the working voltage and creepage/clearan ce capabilities of the si84xx. thes e tables also detail the component standards (ul1577, iec60747, csa 5a), which are readily accepted by certif ication bodies to provide proof for end-system specifications requirements. refer to the end-system specification (61010-1, 60950-1, etc.) requirements before starting any design that uses a digital isolator. 2.4.1. supply bypass the si841x/2x family requires a 1 f bypass capacitor between v dd1 and gnd1 and v dd2 and gnd2. the capacitor should be placed as close as possible to the package. to enhance the robustness of a design, it is further recommended that the user include 100 ? resistors in series with the inputs, outputs, and supply pins if the system is excessively noisy. see "3. errata and design migration guidelines" on page 23 for more details. 2.4.2. pin connections no connect pins are not internally connecte d. they can be left floating, tied to v dd , or tied to gnd. 2.4.3. output pin termination the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series term ination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appr opriately terminated with controlled impedance pcb traces.
si8410/20/21 rev. 1.3 21 2.5. typical perfor mance characteristics the typical performance characteristics de picted in the following diagrams are for information purposes only. refer to tables 3, 4, and 5 for actual specification limits. figure 6. si8410 typical v dd1 supply current vs. data rate 5, 3.3, and 2.70 v operation figure 7. si8420 typical v dd1 supply current vs. data rate 5, 3.3, and 2.70 v operation figure 8. si8421 typical v dd1 or v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 9. si8410 typical v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 10. si8420 typical v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 11. propagation delay vs. temperature 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 0 102030405060708090100110120130140150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 2.70v 3.3v 5 6 7 8 9 10 -40 -20 0 20 40 60 80 100 120 temperature (degrees c) delay (ns) rising edge falling edge
si8410/20/21 22 rev. 1.3 figure 12. si84xx time-dependent dielectric breakdown
si8410/20/21 rev. 1.3 23 3. errata and design migration guidelines the following errata apply to revision c devices only. see "5. ordering guide" on page 25 for more details. no errata exist for revision d devices. 3.1. power supply bypass capaci tors (revision c and revision d) when using the isopro isolators with power supplies > 4.5 v, sufficient vdd bypass capacitors must be present on both the vdd1 and vdd2 pins to ensure the vdd rise time is less than 0.5 v/s (which is > 9 s for a > 4.5 v supply). although rise time is power supply dependent, > 1 f capacitors are required on both power supply pins (vdd1, vdd2) of the isolator device. 3.1.1. resolution this issue has been corrected with re vision d of the device. refer to ?5. ordering guide? for current ordering information. 3.2. latch up imm unity (revision c only) isopro latch up immunity generally exceeds 200 ma per pin. exceptions: certain pins provide < 100 ma of latch- up immunity. to increase latch-up immunity on these pins, 100 ? of equivalent resistance must be included in series with all of the pins listed in table 13. the 100 ? equivalent resistance can be comprised of the source driver's output resistance and a series termination resi stor. the si8410 is not affected by the latch up immunity issue described above. 3.2.1. resolution this issue has been corrected with re vision d of the device. refer to ?5. ordering guide? for current ordering information. table 13. affected ordering part numbers (revision c only) affected ordering part numbers* device revision pin# name pin type si8420sv-c-is, si8421sv-c-is c 3 a2 input or output 7 b1 output *note: sv = speed grade/isolation ra ting (aa, ab, ba, bb).
si8410/20/21 24 rev. 1.3 4. pin descriptions name soic-8 pin# si8410 soic-8 pin# si8420/21 type description v dd1 /nc* 1,3 1 supply side 1 power supply. gnd1 4 4 ground side 1 ground. a1 2 2 digital i/o side 1 digital input or output. a2 na 3 digital i/o side 1 digital input or output. b1 6 7 digital i/o side 2 digital input or output. b2 na 6 digital i/o side 2 digital input or output. v dd2 8 8 supply side 2 power supply. gnd2/nc* 5,7 5 ground side 2 ground. *note: no connect. these pins are not internally connected. th ey can be left floating, tied to vdd or tied to gnd. i s o l a t i o n v dd1 v dd2 a1 rf xmitr b1 rf rcvr gnd1 gnd2 si8410 nb soic-8 v dd1 /nc gnd2/nc i s o l a t i o n v dd1 v dd2 a1 b1 rf xmitr rf rcvr a2 b2 rf xmitr rf rcvr gnd1 gnd2 si8420 nb soic-8 i s o l a t i o n v dd1 v dd2 a1 b1 rf xmitr rf rcvr a2 b2 rf xmitr rf rcvr gnd1 gnd2 si8421 nb soic-8
si8410/20/21 rev. 1.3 25 5. ordering guide revision d devices are recommended for all new designs. table 14. ordering guide for valid opns 1 ordering part number (opn) number of inputs vdd1 side number of inputs vdd2 side maximum data rate (mbps) isolation rating temp range package type revision d devices 2 si8410ab-d-is 1 0 1 2.5 kvrms ?40 to 125 c nb soic-8 si8410bb-d-is 1 0 150 si8420ab-d-is 2 0 1 si8420bb-d-is 2 0 150 si8421ab-d-is 1 1 1 SI8421BB-D-IS 1 1 150 revision c devices 2 si8410ab-c-is 1 0 1 2.5 kvrms ?40 to 125 c nb soic-8 si8410bb-c-is 1 0 150 si8420ab-c-is 2 0 1 si8420bb-c-is 2 0 150 si8421ab-c-is 1 1 1 si8421bb-c-is 1 1 150 notes: 1. all packages are rohs-compliant. moisture sensitivity le vel is msl2a with peak reflow temperature of 260 c according to the jedec industry standard classifications and peak solder temperature. 2. revision c devices are supported for existing designs, but revision d is recommended for all new designs.
si8410/20/21 26 rev. 1.3 6. package outline: 8-pin narrow body soic figure 13 illustrates the package details for the si841x. table 15 lists the val ues for the dimensions shown in the illustration. figure 13. 8-pin small outline integrated circuit (soic) package table 15. package diagram dimensions symbol millimeters min max a 1.35 1.75 a1 0.10 0.25 a2 1.40 ref 1.55 ref b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e 1.27 bsc h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 ? 0 ? 8 ? ?
si8410/20/21 rev. 1.3 27 7. land pattern: 8- pin narrow body soic figure 14 illustrates the recommended land pattern details for the si841x in an 8-pin narrow-body soic. table 16 lists the values for the dimens ions shown in the illustration. figure 14. pcb land pattern: 8-pin narrow body soic table 16. pcm land pattern dimensions (8-pin narrow body soic) dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x173-8n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si8410/20/21 28 rev. 1.3 8. top marking figure 15. isolator top marking table 17. top marking explanations line 1 marking: base part number ordering options (see ordering guide for more information). si84 = isolator product series xy = channel configuration x = # of data channels (2, 1) y = # of reverse channels (1, 0) s = speed grade a = 1 mbps; b = 150 mbps v = insulation rating a = 1 kv; b = 2.5 kv line 2 marking: yy = year ww = workweek assigned by assembly contractor. corresponds to the year and workweek of the mold date. r = product (opn) revision f = wafer fab line 3 marking: circle = 1.1 mm diameter left-justified ?e3? pb-free symbol first two characters of the manufacturing code a = assembly site i = internal code xx = serial lot number last four characters of the manufacturing code si84xysv yywwrf aixx e3
si8410/20/21 rev. 1.3 29 d ocument c hange l ist revision 0.11 to revision 0.21 ? rev 0.21 is the first revision of this document that applies to the new series of ultra low power isolators featuring pinout and func tional compatibility with previous isolator products. ? updated ?1. electrical specifications?. ? updated ?5. ordering guide?. ? added ?8. top marking?. revision 0.21 to revision 0.22 ? updated all specs to re flect latest silicon. revision 0.22 to revision 0.23 ? updated all specs to re flect latest silicon. ? added "3. errata and design migration guidelines" on page 23. revision 0.23 to revision 1.0 ? updated document to reflec t availability of revision d silicon. ? updated tables 3,4, and 5. ?? updated all supply currents and channel-channel skew. ? updated table 2. ?? updated absolute maximum supply voltage. ? updated table 7. ?? updated clearance and creepage dimensions. ? updated "3. errata and design migration guidelines" on page 23. ? updated "5. ordering guide" on page 25. revision 1.0 to revision 1.1 ? updated tables 3, 4, and 5. ?? updated notes in tables to reflect output impedance of 85 : . ?? updated rise and fall time specifications. ?? updated cmti value. revision 1.1 to revision 1.2 ? updated document throughout to include msl improvements to msl2a. ? updated "5. ordering guide" on page 25. ?? updated note 1 in ordering guide table to reflect improvement and compliance to msl2a moisture sensitivity level. revision 1.2 to revision 1.3 ? updated " features" on page 1. ? moved tables 1 and 2 to page 4. ? updated tables 6, 7, 8, and 9. ? updated table 12 footnotes. ? added figure 12, ?si84xx time-dependent dielectric breakdown,? on page 22.
si8410/20/21 30 rev. 1.3 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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